Flash memories have evolved considerably in recent years moving from storage of a single bit in each memory cell to storage of 4 cells per cell, (known as X4), in a recent product by SanDisk Corporation (Milpitas, Calif., USA). Flash memories are commonly referred to as flash and the two terms are used interchangeably in this document. Data is stored in a flash memory in a memory array, also referred to as simply memory.
Memory devices that store 1 bit per cell are known as Single Level Cell (SLC) devices. Strictly speaking, the term SLC is inaccurate, since for storage of 1 bit per cell, the cell must be able to be set to at least 2 different levels, but this term is widely used in the flash community for historical reason that count only the programmed states and not the erase state. In the context of this document, the term SLC is used to designate flash systems able to store 1 bit per cell.
Memory devices that can be set to 3 or more distinguishable physical states (sometimes called voltage thresholds, voltage levels, or simply levels, cell states, or simply states) are referred to as multi level cells (MLC).
In order to ensure reliability of data stored in a flash memory, common practice is to use Error Correcting Codes (ECCs) on the data. Popular ECCs used in flash memory are linear block codes. Such codes operate on blocks of user data, add some redundancy to the data, and generate a codeword, which is stored in the flash memory. Common notation is to denote the number of bits of user data in a block by ‘k’, and the codeword length is denoted as ‘n’. The number of redundancy bits (the bits added by the ECC) is therefore ‘n−k’. The ratio ‘k/n’ is known as the rate of the code, and is denoted by ‘r’. Thus high rate codewords add little redundancy to the data and are able to correct a smaller number of errors, as compared to low rate codes that add more redundancy bits to the data and are able to correct a larger number of errors.
Referring to FIG. 1, a diagram of storing codewords in a flash memory, a common way of storing the codewords in the flash, is by storing the data bits in dedicated data cells, and storing the redundancy bits in dedicated parity cells. In the current figure, cells used to store user data are shown as k, total cells used for the codeword is shown as n, and redundancy cells * are shown also as n−k. Note that although the same notation (n, k, n−k) is typically used to refer to both bits and cells, the use of the notation for bits or cells will be obvious from the context of use.
The number of cells in which the ‘n’ codeword bits are stored is typically n/bpc, where bpc is an acronym for bits per cell (bpc). Typically, the codeword bits are programmed into the memory cells (in flash terminology the writing operation of bits to cells is referred to as programming) in pages. For example, the most significant bits (MSBs) are programmed into a first page, the vector of a next set of bits are programmed into a second page, and the least significant bits (LSBs) are programmed into a last page.
The number of information bits per cell (IBPC) is provided by dividing the size of a block of user data by the size of a codeword and multiplying that ratio by the number of bits per cell (IBPC=[[k/n]*bpc]). IBPC represents the ‘true’ density of the flash. IBPC has a theoretical limit that is determined by the ratio of the voltage window and the read distribution of the states programmed to that window. Thus, increasing the number of states and the redundancy at the same time (such that n/bpc remains constant) maintains the same IBPC, but reduces the programming throughput.
The data bits are typically received from a host external to the flash memory, in host pages of a given length. A desirable feature to simplify programming of the flash memory is that the codeword (or codewords) generated from a single host page occupy an integer multiple of flash pages. For example, consider a case of a host page with a size that is exactly the size of a block of user data divided by the number of bits per cell (k/bpc). Each block of user data is encoded into codewords that are the length of a codeword divided by bpc (n/bpc). In this case, the operation of the flash is relatively simple, since after receiving each host page, the host page is encoded into a codeword of length n/bpc and programmed into a single flash page. When another host page is received, another flash page (word line, WL) in the flash can be programmed.
In contrast, if a codeword generated by the ECC encoder is slightly larger than n/bpc, then part of the codeword can be programmed into a first page of the flash, while the rest of the codeword has to be stored in a temporary cache, and wait for a second codeword. After the second codeword is generated, the second codeword is concatenated to the remainder of the first codeword; then n/bpc bits of the concatenated codewords are programmed into a second page of the flash. The leftover bits will be stored temporarily, etc. This process, including temporary storage of partial codewords, complicates the flash controller, which in turn affects the performance and/or the price of the flash.
For SLC flash memories, high rate codes are sufficient, since SLCs suffer less from read errors, as compared to MLC flash memories that suffer more read errors and require use of lower rate codes. Lower rate codes result in longer codewords. The need for lower rate codes in an MLC as compared to an SLC can be understood from comparing the cell voltage distribution (CVD) of an SLC flash to a CVD of an MLC.
Referring to FIG. 2A, an exemplary plot of probability verse cell threshold voltage (also referred to as threshold voltage) in an SLC flash, 2 states (200, 202) are separated by a large voltage window 204. In the current example, the SLC cell contents may be read by comparing the cell threshold voltage with a voltage of 7 Volts. Even if there is an error of 5 Volts in the cell's actual voltage (relative to the 0 or 10 corresponding verify voltages to which the cell is programmed), the cell can be read without an error.
Referring to FIG. 2B, an exemplary plot of probability verse cell threshold voltage in an MLC flash, 4 states (210, 212, 214, 216) representing 2 bits per cell, are separated by a relatively smaller voltage window 218, as compared to the SLC voltage window 204. In contrast to the SLC memory cell that can have a voltage deviation of 5 volts, in the current MLC example only deviations of up to 2.5 Volts can be tolerated.
Therefore, in SLC flash memories the redundancy cells typically occupy only a small amount of the cell array, (typically 1%-2%), and the impact on the price of the SLC flash memory is limited. In contrast, in MLC flash memories, the code rate may be 0.9 or even less, thus implementing a flash memory with the typical architecture presented in FIG. 1 may have an impact of 10% or more on the price of the flash memory (as compared to the price of the data cells of the flash memory).
A drawback of conventional flash memories is the need to configure the flash memory for a certain level of reliability when the flash memory is first produced, verse a higher level of reliability of the flash memory as production of the flash memory matures. When a new flash memory is designed, the flash memory is targeted to certain reliability measures, and the ECC is set to accommodate the errors anticipated to be generated according to the targeted reliability. For example, if the reliability analysis requires an ECC with a code rate of 0.9, then 10% of the flash area (area of the memory array) is dedicated for the redundancy bits of the ECC codeword.
Over time, improvements are implemented in the flash memory manufacturing process as the manufacturing process reaches maturity, thus increasing the reliability of the flash memories being produced, and requiring only 5% of the flash area to be dedicated for the redundancy bits of the ECC codeword. However, the flash was already manufactured with 10% redundancy, and the cost of changing the flash design is typically prohibitive.
Options for the flash memory after the manufacturing process matures include keeping the current design while paying an extra of 5% in the area of the memory array (and thus in price), or re-designing the memory array which also has a high cost penalty. Moreover, even if a new design can be done for the memory array the ECC, which was originally designed for low rate codes when the flash memory was first produced, may not be optimal for the high rate code of the new flash, so the ECC may also be require re-design.
Another drawback of conventional flash memories is that in some cases, after producing and testing the flash, the design predictions are not exactly met. Sometimes the flash performs better than expected, (thus some flash area was wasted), and a smaller flash could have been designed. This leads to un-necessary higher cost of the flash, which is undesirable but can still be tolerated. Another case is where the flash does not meet the design predictions. This case may have severe consequences, as a new flash may have to be designed, while the first flash design becomes useless.
There is therefore a need to reduce the memory size of an MLC flash and simplify controller operation. There is also a need for maintaining a maximal available IBPC in a flash device while also maximizing the programming throughput of the flash. The present invention addresses these issues, and provides a flexible and efficient way to change the Flash's ECC without requiring costly and radical design changes.